#include <linux/init.h>
#include <linux/clk.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/gpio.h>
#include <linux/spi/spi.h>
#include <asm/mach/map.h>
#include <mach/pmu.h>
#include <mach/clock.h>
#include <mach/board_config.h>
#include <mach/io.h>


/*
 * external oscillator
 * fixed to 24M
 */
static struct fh_clk osc_clk = {
	.name               = "osc_clk",
	.frequency          = OSC_FREQUENCY,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};

static struct fh_clk osc_1m = {
	.name               = "osc_1m",
	.frequency          = 1000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};

static struct fh_clk rtc_32k = {
	.name               = "rtc_32k",
	.frequency          = 32000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};

static struct fh_clk upll_p = {
	.name               = "upll_p",
	.flag               = CLOCK_PLL_P|CLOCK_NOGATE,
	.parent             = {&osc_clk},
	.div_reg_offset     = REG_PMU_UPLL_CTRL1,
	.en_reg_offset      = REG_PMU_UPLL_CTRL0,
	.en_reg_mask        = 0xf0,
};

static struct fh_clk upll_r = {
	.name               = "upll_r",
	.flag               = CLOCK_PLL_R|CLOCK_NOGATE,
	.parent             = {&osc_clk},
	.div_reg_offset     = REG_PMU_UPLL_CTRL1,
	.en_reg_offset      = REG_PMU_UPLL_CTRL0,
	.en_reg_mask        = 0xf,
};

static struct fh_clk epll_p = {
	.name               = "epll_p",
	.flag               = CLOCK_PLL_P|CLOCK_NOGATE,
	.parent             = {&osc_clk},
	.div_reg_offset     = REG_PMU_EPLL_CTRL1,
	.en_reg_offset      = REG_PMU_EPLL_CTRL0,
	.en_reg_mask        = 0xf0,
};

static struct fh_clk epll_r = {
	.name               = "epll_r",
	.flag               = CLOCK_PLL_R|CLOCK_NOGATE,
	.parent             = {&osc_clk},
	.div_reg_offset     = REG_PMU_EPLL_CTRL1,
	.en_reg_offset      = REG_PMU_EPLL_CTRL0,
	.en_reg_mask        = 0xf,
};

static struct fh_clk vpll_p = {
	.name               = "vpll_p",
	.flag               = CLOCK_PLL_P|CLOCK_NOGATE,
	.parent             = {&osc_clk},
	.div_reg_offset     = REG_PMU_VPLL_CTRL1,
	.en_reg_offset      = REG_PMU_VPLL_CTRL0,
	.en_reg_mask        = 0xf0,
};

static struct fh_clk vpll_r = {
	.name               = "vpll_r",
	.flag               = CLOCK_PLL_R|CLOCK_NOGATE,
	.parent             = {&osc_clk},
	.div_reg_offset     = REG_PMU_VPLL_CTRL1,
	.en_reg_offset      = REG_PMU_VPLL_CTRL0,
	.en_reg_mask        = 0xf,
};

static struct fh_clk mpll_p = {
	.name               = "mpll_p",
	.flag               = CLOCK_PLL_P|CLOCK_NOGATE,
	.parent             = {&osc_clk},
	.div_reg_offset     = REG_PMU_MPLL_CTRL1,
	.en_reg_offset      = REG_PMU_MPLL_CTRL0,
	.en_reg_mask        = 0xf0,
};

static struct fh_clk mpll_r = {
	.name               = "mpll_r",
	.flag               = CLOCK_PLL_R|CLOCK_NOGATE,
	.parent             = {&osc_clk},
	.div_reg_offset     = REG_PMU_MPLL_CTRL1,
	.en_reg_offset      = REG_PMU_MPLL_CTRL0,
	.en_reg_mask        = 0xf,
};

static struct fh_clk cpll_p = {
	.name               = "cpll_p",
	.flag               = CLOCK_PLL_P|CLOCK_NOGATE,
	.parent             = {&osc_clk},
	.div_reg_offset     = REG_PMU_CPLL_CTRL1,
	.en_reg_offset      = REG_PMU_CPLL_CTRL0,
	.en_reg_mask        = 0xf0,
};

static struct fh_clk cpll_r = {
	.name               = "cpll_r",
	.flag               = CLOCK_PLL_R|CLOCK_NOGATE,
	.parent             = {&osc_clk},
	.div_reg_offset     = REG_PMU_CPLL_CTRL1,
	.en_reg_offset      = REG_PMU_CPLL_CTRL0,
	.en_reg_mask        = 0xf,
};

static struct fh_clk dpll_p = {
	.name               = "dpll_p",
	.flag               = CLOCK_PLL_P|CLOCK_NOGATE,
	.parent             = {&osc_clk},
	.div_reg_offset     = REG_PMU_DPLL_CTRL1,
	.en_reg_offset      = REG_PMU_DPLL_CTRL0,
	.en_reg_mask        = 0xf0,
};

static struct fh_clk dpll_r = {
	.name               = "dpll_r",
	.flag               = CLOCK_PLL_R|CLOCK_NOGATE,
	.parent             = {&osc_clk},
	.div_reg_offset     = REG_PMU_DPLL_CTRL1,
	.en_reg_offset      = REG_PMU_DPLL_CTRL0,
	.en_reg_mask        = 0xf,
};


/*PLL_SYS*/

static struct fh_clk dpll_792m = {
	.name               = "dpll_792m",
	.frequency          = 792000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};

static struct fh_clk epll_792m = {
	.name               = "epll_792m",
	.frequency          = 792000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};

static struct fh_clk mpll_450m = {
	.name               = "mpll_450m",
	.frequency          = 450000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};

static struct fh_clk vpll_648m = {
	.name               = "vpll_648m",
	.frequency          = 648000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};

static struct fh_clk upll_1536m = {
	.name               = "upll_1536m",
	.frequency          = 1536000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};

static struct fh_clk spll_297m = {
	.name               = "spll_297m",
	.frequency          = 297100000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};


/*top*/
static struct fh_clk vpll_324m_top = {
	.name               = "vpll_324m_top",
	.frequency          = 324000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};

static struct fh_clk mpll_50m_top = {
	.name               = "mpll_50m_top",
	.frequency          = 50000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};

static struct fh_clk mpll_25m_top = {
	.name               = "mpll_25m_top",
	.frequency          = 25000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};

static struct fh_clk upll_768m_top = {
	.name               = "upll_768m_top",
	.frequency          = 768000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};

static struct fh_clk upll_512m_top = {
	.name               = "upll_512m_top",
	.frequency          = 512000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};

static struct fh_clk upll_128m_top = {
	.name               = "upll_128m_top",
	.frequency          = 128000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};

static struct fh_clk upll_48m_top = {
	.name               = "upll_48m_top",
	.frequency          = 48000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};


static struct fh_clk epll_400m_top = {
	.name               = "epll_400m_top",
	.frequency          = 400000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};

static struct fh_clk epll_200m_top = {
	.name               = "epll_200m_top",
	.frequency          = 200000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};

static struct fh_clk epll_100m_top = {
	.name               = "epll_100m_top",
	.frequency          = 100000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};

/*dmc*/
static struct fh_clk epll_400m_dmc = {
	.name               = "epll_400m_dmc",
	.frequency          = 400000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};

static struct fh_clk mpll_50m_dmc = {
	.name               = "mpll_50m_dmc",
	.frequency          = 50000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};
/* vdu */
static struct fh_clk vpll_324m_vdu = {
	.name               = "vpll_324m_vdu",
	.frequency          = 324000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};

static struct fh_clk vpll_54m_vdu = {
	.name               = "vpll_54m_vdu",
	.frequency          = 54000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};

static struct fh_clk vpll_40m_vdu = {
	.name               = "vpll_40m_vdu",
	.frequency          = 40500000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};

static struct fh_clk vpll_27m_vdu = {
	.name               = "vpll_27m_vdu",
	.frequency          = 27000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};

static struct fh_clk vpll_13m_vdu = {
	.name               = "vpll_13m_vdu",
	.frequency          = 13500000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};

static struct fh_clk mpll_50m_vdu = {
	.name               = "mpll_50m_vdu",
	.frequency          = 50000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};

static struct fh_clk mpll_25m_vdu = {
	.name               = "mpll_25m_vdu",
	.frequency          = 25000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};

static struct fh_clk mpll_22m_vdu = {
	.name               = "mpll_22m_vdu",
	.frequency          = 22500000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};

static struct fh_clk mpll_15m_vdu = {
	.name               = "mpll_15m_vdu",
	.frequency          = 15000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};


static struct fh_clk epll_400m_vdu = {
	.name               = "epll_400m_vdu",
	.frequency          = 400000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};

static struct fh_clk epll_200m_vdu = {
	.name               = "epll_200m_vdu",
	.frequency          = 200000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};

static struct fh_clk epll_100m_vdu = {
	.name               = "epll_100m_vdu",
	.frequency          = 100000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};


static struct fh_clk epll_67m_vdu = {
	.name               = "epll_67m_vdu",
	.frequency          = 66700000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};

static struct fh_clk upll_128m_vdu = {
	.name               = "upll_128m_vdu",
	.frequency          = 128000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};

/*nnp*/

static struct fh_clk nnp_533m = {
	.name               = "nnp_533m",
	.frequency          = 533000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};

static struct fh_clk nnp_648m = {
	.name               = "nnp_648m",
	.frequency          = 648000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};

static struct fh_clk nnp_768m = {
	.name               = "nnp_768m",
	.frequency          = 768000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};
static struct fh_clk nnp_792m = {
	.name               = "nnp_792m",
	.frequency          = 792000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};
static struct fh_clk nnp_20m = {
	.name               = "nnp_20m",
	.frequency          = 20000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};

static struct fh_clk nnp_50m = {
	.name               = "nnp_50m",
	.frequency          = 50000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};

static struct fh_clk nnp_100m = {
	.name               = "nnp_100m",
	.frequency          = 100000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};

static struct fh_clk nnp_150m = {
	.name               = "nnp_150m",
	.frequency          = 150000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};

static struct fh_clk nnp_200m = {
	.name               = "nnp_200m",
	.frequency          = 200000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};

static struct fh_clk nnp_400m = {
	.name               = "nnp_400m",
	.frequency          = 400000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};




/*veu*/

static struct fh_clk mpll_50m_veu = {
	.name               = "mpll_50m_veu",
	.frequency          = 50000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};

/*isp*/

static struct fh_clk epll_200m_isp = {
	.name               = "epll_200m_isp",
	.frequency          = 200000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};

static struct fh_clk epll_100m_isp = {
	.name               = "epll_100m_isp",
	.frequency          = 100000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};

static struct fh_clk mpll_50m_isp = {
	.name               = "mpll_50m_isp",
	.frequency          = 50000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};

static struct fh_clk vpll_81m_isp = {
	.name               = "vpll_81m_isp",
	.frequency          = 81000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};

/*cpu*/
static struct fh_clk epll_400m_cpu = {
	.name               = "epll_400m_cpu",
	.frequency          = 400000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};


static struct fh_clk epll_200m_cpu = {
	.name               = "epll_200m_cpu",
	.frequency          = 200000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};

static struct fh_clk epll_100m_cpu = {
	.name               = "epll_100m_cpu",
	.frequency          = 100000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};

static struct fh_clk mpll_50m_cpu = {
	.name               = "mpll_50m_cpu",
	.frequency          = 50000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};
static struct fh_clk tmr0_clk = {
	.name               = "tmr0_clk",
	.frequency          = 24000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};
static struct fh_clk tmr1_clk = {
	.name               = "tmr1_clk",
	.frequency          = 24000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};
static struct fh_clk tmr2_clk = {
	.name               = "tmr2_clk",
	.frequency          = 24000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};


static struct fh_clk pts_clk = {
	.name               = "pts_clk",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&osc_clk, &mpll_25m_top, &mpll_50m_top},
	.prediv             = 1,
	.sel_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x28,
	.sel_reg_mask       = 0x3,
	.div_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x28,
	.div_reg_mask       = 0x3f00,
	/*ckg_pts_en*/
	.en_reg_offset		= VA_CEN_GLB_APB_REG_BASE + 0x1c,
	.en_reg_mask		= 0x4,
};

static struct fh_clk ephy_clk = {
	.name               = "ephy_clk",
	.flag               = CLOCK_NOGATE,
	.parent             = {&mpll_50m_top},
	.prediv             = 1,
	.div_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x2c,
	.div_reg_mask       = 0x300,
};

static struct fh_clk glb_apb = {
	.name               = "glb_apb",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&osc_clk, &mpll_50m_top, &epll_100m_top,
							&epll_200m_top},
	.prediv             = 1,
	.sel_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x30,
	.sel_reg_mask       = 0x3,
	/*ckg_glb_apb_isp_en*/
	.en_reg_offset		= VA_CEN_GLB_APB_REG_BASE + 0x78,
	.en_reg_mask		= 0x4,
};

static struct fh_clk glb_vicap = {
	.name               = "glb_vicap",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&osc_clk, &vpll_324m_top, &epll_400m_top,
							&mpll_450m, &cpll_r},
	.prediv             = 1,
	.sel_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x34,
	.sel_reg_mask       = 0x7,
	/*ckg_glb_vicap_isp_en*/
	.en_reg_offset		= VA_CEN_GLB_APB_REG_BASE + 0x78,
	.en_reg_mask		= 0x80,
	.div_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x34,
	.div_reg_mask       = 0xf00,
	.def_rate           = 504000000,
};
static struct fh_clk glb_cpu2lvd = {
	.name               = "glb_cpu2lvd",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&osc_clk, &epll_200m_top, &vpll_324m_top,
							&epll_400m_top},
	.prediv             = 1,
	.en_reg_offset		= VA_VEU_SYS_AHB_REG_BASE + 0x0,
	.en_reg_mask		= 0x10,
	.sel_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x38,
	.sel_reg_mask       = 0x3,
};

static struct fh_clk glb_vdu = {
	.name               = "glb_vdu",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&osc_clk, &epll_100m_top, &epll_200m_top,
							&vpll_324m_top},
	.prediv             = 1,
	.sel_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x3c,
	.sel_reg_mask       = 0x3,
	.en_reg_offset		= VA_VDU_SYS_APB_REG_BASE + 0x0,
	.en_reg_mask		= 0x800,
	.div_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x3c,
	.div_reg_mask       = 0xf00,
	.def_rate           = 324000000,
};

static struct fh_clk glb_vou = {
	.name               = "glb_vou",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&osc_clk, &epll_100m_top, &epll_200m_top,
							&vpll_324m_top},
	.prediv             = 1,
	.sel_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x40,
	.sel_reg_mask       = 0x3,
	.en_reg_offset		= VA_VDU_SYS_APB_REG_BASE + 0x0,
	.en_reg_mask		= 0x400,
	.div_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x40,
	.div_reg_mask       = 0xf00,
	.def_rate           = 324000000,
};

static struct fh_clk glb_isp = {
	.name               = "glb_isp",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&osc_clk, &epll_100m_top, &epll_200m_top,
						&upll_1536m, &vpll_324m_top},
	.prediv             = 1,
	.sel_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x44,
	.sel_reg_mask       = 0x7,
	/*ckg_glb_isp_isp_en*/
	.en_reg_offset		= VA_CEN_GLB_APB_REG_BASE + 0x78,
	.en_reg_mask		= 0x2000,
	.div_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x44,
	.div_reg_mask       = 0xf00,
	.def_rate           = 324000000,
};

static struct fh_clk glb_veu = {
	.name               = "glb_veu",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&epll_400m_top, &mpll_450m, &upll_512m_top,
						&vpll_648m, &upll_768m_top},
	.prediv             = 1,
	.sel_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x48,
	.sel_reg_mask       = 0x7,
	/*ckg_glb_veu_veu_en*/
	.en_reg_offset		= VA_CEN_GLB_APB_REG_BASE + 0x78,
	.en_reg_mask		= 0x10000,
	.div_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x48,
	.div_reg_mask       = 0xf00,
	.def_rate           = 768000000,
};
static struct fh_clk ave_bond_ave = {
	.name               = "ave_bond_ave",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&osc_clk, &spll_297m},
	.prediv             = 1,
	.sel_reg_offset     = VA_VDU_SYS_APB_REG_BASE + 0x8,
	.sel_reg_mask       = 0x8000000,
	/*ckg_ave_en*/
	.en_reg_offset		= VA_VDU_SYS_APB_REG_BASE + 0x8,
	.en_reg_mask		= 0x4000000,
};
static struct fh_clk ahb_ave_bond = {
	.name               = "ahb_ave_bond",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&osc_clk, &mpll_50m_vdu, &epll_100m_vdu,
							&epll_200m_vdu},
	.prediv             = 1,
	.sel_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x30,
	.sel_reg_mask       = 0x3,
	/*ckg_ahb_ave_en*/
	.en_reg_offset		= VA_VDU_SYS_APB_REG_BASE + 0xc,
	.en_reg_mask		= 0x8000,
};
static struct fh_clk ahb_bgm = {
	.name               = "ahb_bgm",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&osc_clk, &mpll_50m_vdu, &epll_100m_vdu,
							&epll_200m_vdu},
	.prediv             = 1,
	.sel_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x30,
	.sel_reg_mask       = 0x3,
	/*ckg_ahb_bgm_en*/
	.en_reg_offset		= VA_VDU_SYS_APB_REG_BASE + 0xc,
	.en_reg_mask		= 0x20000,
};
static struct fh_clk bgm_clk = {
	.name               = "bgm_clk",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&osc_clk, &epll_100m_vdu, &epll_200m_vdu,
							&vpll_324m_vdu},
	.prediv             = 1,
	.sel_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x3c,
	.sel_reg_mask       = 0x3,
	/*ckg_bgm_en*/
	.en_reg_offset		= VA_VDU_SYS_APB_REG_BASE + 0x8,
	.en_reg_mask		= 0x2,
	.def_rate           = 324000000,
};
static struct fh_clk g2d_clk = {
	.name               = "g2d_clk",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&osc_clk, &epll_100m_vdu, &epll_200m_vdu,
							&vpll_324m_vdu},
	.prediv             = 1,
	.sel_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x3c,
	.sel_reg_mask       = 0x3,
	/*ckg_g2d_en*/
	.en_reg_offset		= VA_VDU_SYS_APB_REG_BASE + 0x8,
	.en_reg_mask		= 0x1,
};
static struct fh_clk axi_hkisp_mst = {
	.name               = "axi_hkisp_mst",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&osc_clk, &epll_100m_vdu, &epll_200m_vdu,
							&vpll_324m_vdu},
	.prediv             = 1,
	.sel_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x40,
	.sel_reg_mask       = 0x3,
	/*ckg_axi_hkisp_mst_en*/
	.en_reg_offset		= VA_VDU_SYS_APB_REG_BASE + 0x8,
	.en_reg_mask		= 0x1000,
	.div_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x40,
	.div_reg_mask       = 0xf00,
};
static struct fh_clk ahb_ive = {
	.name               = "ahb_ive",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&osc_clk, &mpll_50m_vdu, &epll_100m_vdu,
							&epll_200m_vdu},
	.prediv             = 1,
	.sel_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x30,
	.sel_reg_mask       = 0x3,
	/*ckg_ahb_ive_en*/
	.en_reg_offset		= VA_VDU_SYS_APB_REG_BASE + 0xc,
	.en_reg_mask		= 0x10000,
};
static struct fh_clk ive_clk = {
	.name               = "ive_clk",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&osc_clk, &epll_100m_vdu, &epll_200m_vdu,
							&vpll_324m_vdu},
	.prediv             = 1,
	.sel_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x3c,
	.sel_reg_mask       = 0x3,
	/*ckg_ive_en*/
	.en_reg_offset		= VA_VDU_SYS_APB_REG_BASE + 0x8,
	.en_reg_mask		= 0x4,
	.div_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x3c,
	.div_reg_mask       = 0xf00,
};
static struct fh_clk jpeg_clk = {
	.name               = "jpeg_clk",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&osc_clk, &vpll_324m_vdu, &epll_400m_vdu,
							&mpll_450m},
	.prediv             = 1,
	.sel_reg_offset     = VA_VDU_SYS_APB_REG_BASE + 0x0,
	.sel_reg_mask       = 0x3,
	/*ckg_jpg_en*/
	.en_reg_offset      = VA_VDU_SYS_APB_REG_BASE + 0x8,
	.en_reg_mask        = 0x20,
	.div_reg_offset     = VA_VDU_SYS_APB_REG_BASE + 0x120,
	.div_reg_mask       = 0xf0,
	.def_rate           = 450000000,
};
static struct fh_clk ahb_jpeg = {
	.name               = "ahb_jpeg",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&osc_clk, &mpll_50m_vdu, &epll_100m_vdu,
							&epll_200m_vdu},
	.prediv             = 1,
	.sel_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x30,
	.sel_reg_mask       = 0x3,
	/*ckg_ahb_jpg_en*/
	.en_reg_offset		= VA_VDU_SYS_APB_REG_BASE + 0xc,
	.en_reg_mask		= 0x40000,
};
static struct fh_clk kcf_clk = {
	.name               = "kcf_clk",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&osc_clk, &vpll_324m_vdu, &epll_400m_vdu,
							&mpll_450m},
	.prediv             = 1,
	.sel_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x3c,
	.sel_reg_mask       = 0x3,
	/*ckg_kcf_en*/
	.en_reg_offset      = VA_VDU_SYS_APB_REG_BASE + 0x8,
	.en_reg_mask        = 0x10,
	.div_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x3c,
	.div_reg_mask       = 0xf00,
};

static struct fh_clk ahb_tve_bond = {
	.name               = "ahb_tve_bond",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&osc_clk, &mpll_50m_vdu, &epll_100m_vdu,
							&epll_200m_vdu},
	.prediv             = 1,
	.sel_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x30,
	.sel_reg_mask       = 0x3,
	/*ckg_ahb_tve_en*/
	.en_reg_offset		= VA_VDU_SYS_APB_REG_BASE + 0xc,
	.en_reg_mask		= 0x4000,
};
static struct fh_clk vou_sif = {
	.name               = "vou_sif",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&osc_clk, &spll_297m},
	.prediv             = 1,
	.sel_reg_offset     = VA_VDU_SYS_APB_REG_BASE + 0xc,
	.sel_reg_mask       = 0x100,
	/*ckg_vou_sif_en*/
	.en_reg_offset		= VA_VDU_SYS_APB_REG_BASE + 0xc,
	.en_reg_mask		= 0x80,
	.def_rate			= 297100000,
};
static struct fh_clk vou_mif = {
	.name               = "vou_mif",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&osc_clk, &spll_297m},
	.prediv             = 1,
	.sel_reg_offset     = VA_VDU_SYS_APB_REG_BASE + 0xc,
	.sel_reg_mask       = 0x20,
	/*ckg_vou_mif_en*/
	.en_reg_offset		= VA_VDU_SYS_APB_REG_BASE + 0xc,
	.en_reg_mask		= 0x10,
};

static struct fh_clk dsi_pixel_clk = {
	.name               = "dsi_pixel_clk",
	.frequency          = 432000000,
	.flag               = CLOCK_FIXED | CLOCK_NOGATE,
};

static struct fh_clk vou_mif_pad_sel = {
	.name               = "vou_mif_pad_sel",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&vou_mif, &dsi_pixel_clk},
	.prediv             = 1,
	.sel_reg_offset     = VA_VDU_SYS_APB_REG_BASE + 0xc,
	.sel_reg_mask       = 0x40,
};
static struct fh_clk vdec660_bond = {
	.name               = "vdec660_bond",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&osc_clk, &epll_100m_vdu, &epll_200m_vdu,
							&vpll_324m_vdu},
	.prediv             = 1,
	.sel_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x3c,
	.sel_reg_mask       = 0x3,
	/*ckg_vdec660_en*/
	.en_reg_offset		= VA_VDU_SYS_APB_REG_BASE + 0x8,
	.en_reg_mask		= 0x8,
	.div_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x3c,
	.div_reg_mask       = 0xf00,
};

static struct fh_clk vou460_clk = {
	.name               = "vou460_clk",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&osc_clk, &epll_100m_vdu, &epll_200m_vdu,
							&vpll_324m_vdu},
	.prediv             = 1,
	.sel_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x40,
	.sel_reg_mask       = 0x3,
	/*ckg_vdec660_en*/
	.en_reg_offset		= VA_VDU_SYS_APB_REG_BASE + 0x8,
	.en_reg_mask		= 0x800,
	.div_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x40,
	.div_reg_mask       = 0xf00,
};

static struct fh_clk vppu460_clk = {
	.name               = "vppu460_clk",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&osc_clk, &epll_200m_vdu, &vpll_324m_vdu,
							&epll_400m_vdu},
	.prediv             = 1,
	.en_reg_offset		= VA_VDU_SYS_APB_REG_BASE + 0x8,
	.en_reg_mask		= 0x40,
	.sel_reg_offset     = VA_VDU_SYS_APB_REG_BASE + 0x0,
	.sel_reg_mask       = 0xc,
	.div_reg_offset     = VA_VDU_SYS_APB_REG_BASE + 0x11c,
	.div_reg_mask       = 0xf,
	.def_rate           = 400000000,
};
static struct fh_clk nnp_clk = {
	.name               = "nnp_clk",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&osc_clk, &nnp_533m, &nnp_648m,
							&nnp_768m, &nnp_792m},
	.prediv             = 1,
	/*ckg_glb_nnp_en*/
	.en_reg_offset		= VA_NNP_SYS_APB_REG_BASE + 0x100,
	.en_reg_mask		= 0x2,
	.sel_reg_offset     = VA_NNP_SYS_APB_REG_BASE + 0x100,
	.sel_reg_mask       = 0x380,
	.div_reg_offset     = VA_NNP_SYS_APB_REG_BASE + 0x100,
	.div_reg_mask       = 0x3c000,
	.def_rate           = 533000000,
};

static struct fh_clk top_apb = {
	.name               = "top_apb",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NOGATE | CLOCK_NODIV,
	.parent             = {&osc_clk, &mpll_50m_top, &epll_100m_top},
	.prediv             = 1,
	.sel_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x4c,
	.sel_reg_mask       = 0x3,
};
static struct fh_clk sfc_clk = {
	.name               = "sfc_clk",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&osc_clk, &nnp_50m, &nnp_100m,
							&nnp_150m, &nnp_200m},
	.prediv             = 1,
	.en_reg_offset		= VA_NNP_SYS_APB_REG_BASE + 0x600,
	.en_reg_mask		= 0x2,
	.en_reg_offset1		= VA_NNP_SYS_APB_REG_BASE + 0x600,
	.en_reg_mask1		= 0x4,
	.sel_reg_offset     = VA_NNP_SYS_APB_REG_BASE + 0x600,
	.sel_reg_mask       = 0x38,
};

static struct fh_clk spi0_clk = {
	.name               = "spi0_clk",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&osc_clk, &mpll_50m_top, &epll_100m_top},
	.prediv             = 1,
	.sel_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x50,
	.sel_reg_mask       = 0x3,
	.en_reg_offset		= VA_TOP_SYS_APB_REG_BASE + 0x0,
	.en_reg_mask		= 0x200000,
	.en_reg_offset1		= VA_TOP_SYS_APB_REG_BASE + 0x4,
	.en_reg_mask1		= 0x40000,

};

static struct fh_clk spi1_clk = {
	.name               = "spi1_clk",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&osc_clk, &mpll_50m_top, &epll_100m_top},
	.prediv             = 1,
	.sel_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x54,
	.sel_reg_mask       = 0x3,
	.en_reg_offset		= VA_TOP_SYS_APB_REG_BASE + 0x0,
	.en_reg_mask		= 0x400000,
	.en_reg_offset1		= VA_TOP_SYS_APB_REG_BASE + 0x4,
	.en_reg_mask1		= 0x80000,
};

static struct fh_clk syst_clk = {
	.name               = "syst_clk",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&rtc_32k, &osc_1m, &osc_clk},
	.prediv             = 1,
	.div_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x58,
	.div_reg_mask       = 0xff00,
	.sel_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x58,
	.sel_reg_mask       = 0x3,
	.en_reg_offset		= VA_TOP_SYS_APB_REG_BASE + 0x0,
	.en_reg_mask		= 0x1,
	.en_reg_offset1		= VA_TOP_SYS_APB_REG_BASE + 0x4,
	.en_reg_mask1		= 0x1,
};

static struct fh_clk uart0_clk = {
	.name               = "uart0_clk",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&osc_clk, &mpll_50m_top, &epll_100m_top,
							&upll_128m_top,},
	.prediv             = 1,
	.sel_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x74,
	.sel_reg_mask       = 0x3,
	.div_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x74,
	.div_reg_mask       = 0x700,
	.en_reg_offset		= VA_TOP_SYS_APB_REG_BASE + 0x0,
	.en_reg_mask		= 0x1000000,
	.en_reg_offset1		= VA_TOP_SYS_APB_REG_BASE + 0x4,
	.en_reg_mask1		= 0x800000,
};
static struct fh_clk uart1_clk = {
	.name               = "uart1_clk",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&osc_clk, &mpll_50m_top, &epll_100m_top,
							&upll_128m_top,},
	.prediv             = 1,
	.sel_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x78,
	.sel_reg_mask       = 0x3,
	.div_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x78,
	.div_reg_mask       = 0x700,
	.en_reg_offset		= VA_TOP_SYS_APB_REG_BASE + 0x0,
	.en_reg_mask		= 0x2000000,
	.en_reg_offset1		= VA_TOP_SYS_APB_REG_BASE + 0x4,
	.en_reg_mask1		= 0x1000000,
};
static struct fh_clk uart2_clk = {
	.name               = "uart2_clk",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&osc_clk, &mpll_50m_top, &epll_100m_top,
							&upll_128m_top,},
	.prediv             = 1,
	.sel_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x7c,
	.sel_reg_mask       = 0x3,
	.div_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x7c,
	.div_reg_mask       = 0x700,
	.en_reg_offset		= VA_TOP_SYS_APB_REG_BASE + 0x0,
	.en_reg_mask		= 0x4000000,
	.en_reg_offset1		= VA_TOP_SYS_APB_REG_BASE + 0x4,
	.en_reg_mask1		= 0x2000000,

};

static struct fh_clk uart3_clk = {
	.name               = "uart3_clk",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&osc_clk, &mpll_50m_top, &epll_100m_top,
							&upll_128m_top,},
	.prediv             = 1,
	.sel_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x80,
	.sel_reg_mask       = 0x3,
	.div_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x80,
	.div_reg_mask       = 0x700,
	.en_reg_offset      = VA_TOP_SYS_APB_REG_BASE + 0x0,
	.en_reg_mask        = 0x8000000,
	.en_reg_offset1		= VA_TOP_SYS_APB_REG_BASE + 0x4,
	.en_reg_mask1		= 0x4000000,
};

static struct fh_clk uart4_clk = {
	.name               = "uart4_clk",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&osc_clk, &mpll_50m_top, &epll_100m_top,
							&upll_128m_top,},
	.prediv             = 1,
	.sel_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x84,
	.sel_reg_mask       = 0x3,
	.div_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x84,
	.div_reg_mask       = 0x700,
	.en_reg_offset      = VA_TOP_SYS_APB_REG_BASE + 0x0,
	.en_reg_mask        = 0x10000000,
	.en_reg_offset1		= VA_TOP_SYS_APB_REG_BASE + 0x4,
	.en_reg_mask1		= 0x8000000,
};

static struct fh_clk uart5_clk = {
	.name               = "uart5_clk",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&osc_clk, &mpll_50m_top, &epll_100m_top,
							&upll_128m_top,},
	.prediv             = 1,
	.sel_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x88,
	.sel_reg_mask       = 0x3,
	.div_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x88,
	.div_reg_mask       = 0x700,
	.en_reg_offset      = VA_TOP_SYS_APB_REG_BASE + 0x0,
	.en_reg_mask        = 0x20000000,
	.en_reg_offset1		= VA_TOP_SYS_APB_REG_BASE + 0x4,
	.en_reg_mask1		= 0x10000000,
};

static struct fh_clk i2c0_clk = {
	.name               = "i2c0_clk",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&osc_clk, &epll_100m_top, &upll_128m_top,},
	.prediv             = 1,
	.sel_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x8c,
	.sel_reg_mask       = 0x3,
	.div_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x8c,
	.div_reg_mask       = 0x700,
	.en_reg_offset		= VA_TOP_SYS_APB_REG_BASE + 0x0,
	.en_reg_mask		= 0x4000,
	.en_reg_offset1		= VA_TOP_SYS_APB_REG_BASE + 0x4,
	.en_reg_mask1		= 0x800,
};

static struct fh_clk i2c1_clk = {
	.name               = "i2c1_clk",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&osc_clk, &epll_100m_top, &upll_128m_top,},
	.prediv             = 1,
	.sel_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x90,
	.sel_reg_mask       = 0x3,
	.div_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x90,
	.div_reg_mask       = 0x700,
	.en_reg_offset		= VA_TOP_SYS_APB_REG_BASE + 0x0,
	.en_reg_mask		= 0x8000,
	.en_reg_offset1		= VA_TOP_SYS_APB_REG_BASE + 0x4,
	.en_reg_mask1		= 0x1000,
};

static struct fh_clk i2c2_clk = {
	.name               = "i2c2_clk",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&osc_clk, &epll_100m_top, &upll_128m_top,},
	.prediv             = 1,
	.sel_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x94,
	.sel_reg_mask       = 0x3,
	.div_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x94,
	.div_reg_mask       = 0x700,
	.en_reg_offset		= VA_TOP_SYS_APB_REG_BASE + 0x0,
	.en_reg_mask		= 0x10000,
	.en_reg_offset1		= VA_TOP_SYS_APB_REG_BASE + 0x4,
	.en_reg_mask1		= 0x2000,
};

static struct fh_clk i2c3_clk = {
	.name               = "i2c3_clk",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&osc_clk, &epll_100m_top, &upll_128m_top,},
	.prediv             = 1,
	.sel_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x98,
	.sel_reg_mask       = 0x3,
	.div_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x98,
	.div_reg_mask       = 0x700,
	.en_reg_offset		= VA_TOP_SYS_APB_REG_BASE + 0x0,
	.en_reg_mask		= 0x20000,
	.en_reg_offset1		= VA_TOP_SYS_APB_REG_BASE + 0x4,
	.en_reg_mask1		= 0x4000,
};

static struct fh_clk i2c4_clk = {
	.name               = "i2c4_clk",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&osc_clk, &epll_100m_top, &upll_128m_top,},
	.prediv             = 1,
	.sel_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x9c,
	.sel_reg_mask       = 0x3,
	.div_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0x9c,
	.div_reg_mask       = 0x700,
	.en_reg_offset		= VA_TOP_SYS_APB_REG_BASE + 0x0,
	.en_reg_mask		= 0x40000,
	.en_reg_offset1		= VA_TOP_SYS_APB_REG_BASE + 0x4,
	.en_reg_mask1		= 0x8000,
};

static struct fh_clk i2c5_clk = {
	.name               = "i2c5_clk",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&osc_clk, &epll_100m_top, &upll_128m_top,},
	.prediv             = 1,
	.sel_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0xa0,
	.sel_reg_mask       = 0x3,
	.div_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0xa0,
	.div_reg_mask       = 0x700,
	.en_reg_offset		= VA_TOP_SYS_APB_REG_BASE + 0x0,
	.en_reg_mask		= 0x80000,
	.en_reg_offset1		= VA_TOP_SYS_APB_REG_BASE + 0x4,
	.en_reg_mask1		= 0x10000,
};

static struct fh_clk pwm_clk = {
	.name               = "pwm_clk",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&osc_clk, &mpll_50m_top, &epll_100m_top,},
	.prediv             = 1,
	.sel_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0xa4,
	.sel_reg_mask       = 0x3,
	.en_reg_offset		= VA_TOP_SYS_APB_REG_BASE + 0x0,
	.en_reg_mask		= 0x100000,
	.en_reg_offset1		= VA_TOP_SYS_APB_REG_BASE + 0x4,
	.en_reg_mask1		= 0x20000,
};

static struct fh_clk hash_clk = {
	.name               = "hash_clk",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&osc_clk, &mpll_50m_top, &epll_100m_top,},
	.prediv             = 1,
	.sel_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0xa8,
	.sel_reg_mask       = 0x3,
	.en_reg_offset		= VA_TOP_SYS_APB_REG_BASE + 0x0,
	.en_reg_mask		= 0x2000,
	.en_reg_offset1		= VA_TOP_SYS_APB_REG_BASE + 0x4,
	.en_reg_mask1		= 0x400,
};

static struct fh_clk src_clk = {
	.name               = "src_clk",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&osc_clk, &mpll_50m_top, &epll_100m_top},
	.prediv             = 1,
	.sel_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0xac,
	.sel_reg_mask       = 0x3,
	.en_reg_offset		= VA_TOP_SYS_APB_REG_BASE + 0x0,
	.en_reg_mask		= 0x400,
	.en_reg_offset1		= VA_TOP_SYS_APB_REG_BASE + 0x4,
	.en_reg_mask1		= 0x80,
};

static struct fh_clk rsa_clk = {
	.name               = "rsa_clk",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&osc_clk, &mpll_50m_top, &epll_100m_top,
						&mpll_450m},
	.prediv             = 1,
	.sel_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0xb0,
	.sel_reg_mask       = 0x3,
	.en_reg_offset		= VA_TOP_SYS_APB_REG_BASE + 0x0,
	.en_reg_mask		= 0x1000,
	.en_reg_offset1		= VA_TOP_SYS_APB_REG_BASE + 0x4,
	.en_reg_mask1		= 0x200,
};

static struct fh_clk trng_clk = {
	.name               = "trng_clk",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&osc_clk, &mpll_50m_top, &epll_100m_top,},
	.prediv             = 1,
	.sel_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0xb4,
	.sel_reg_mask       = 0x3,
	.en_reg_offset		= VA_TOP_SYS_APB_REG_BASE + 0x0,
	.en_reg_mask		= 0x800,
	.en_reg_offset1		= VA_TOP_SYS_APB_REG_BASE + 0x4,
	.en_reg_mask1		= 0x100,
};

static struct fh_clk gpio_db_clk = {
	.name               = "gpio_db_clk",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&rtc_32k, &osc_1m, &osc_clk, &mpll_50m_top},
	.prediv             = 1,
	.div_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0xb8,
	.div_reg_mask       = 0xff00,
	.sel_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0xb8,
	.sel_reg_mask       = 0x3,
	.en_reg_offset		= VA_TOP_SYS_APB_REG_BASE + 0x0,
	.en_reg_mask		= 0x40000000,
};

static struct fh_clk sensor0_clk = {
	.name               = "sensor0_clk",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&osc_clk, &upll_48m_top, &spll_297m},
	.prediv             = 1,
	.sel_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0xc0,
	.sel_reg_mask       = 0x3,
	.div_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0xc0,
	.div_reg_mask       = 0xf00,
	.en_reg_offset		= VA_CEN_GLB_APB_REG_BASE + 0x194,
	.en_reg_mask		= 0x1,
};

static struct fh_clk sensor1_clk = {
	.name               = "sensor1_clk",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&osc_clk, &upll_48m_top, &spll_297m},
	.prediv             = 1,
	.sel_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0xc4,
	.sel_reg_mask       = 0x3,
	.div_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0xc4,
	.div_reg_mask       = 0xf00,
	.en_reg_offset		= VA_CEN_GLB_APB_REG_BASE + 0x194,
	.en_reg_mask		= 0x2,
};

static struct fh_clk sensor2_clk = {
	.name               = "sensor2_clk",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&osc_clk, &upll_48m_top, &spll_297m},
	.prediv             = 1,
	.sel_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0xc8,
	.sel_reg_mask       = 0x3,
	.div_reg_offset     = VA_TOP_CLK_RF_REG_BASE + 0xc8,
	.div_reg_mask       = 0xf00,
	.en_reg_offset		= VA_CEN_GLB_APB_REG_BASE + 0x194,
	.en_reg_mask		= 0x4,
};

static struct fh_clk cpu_clk = {
	.name               = "cpu_clk",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NOGATE | CLOCK_NODIV,
	.parent             = {&osc_clk, &epll_400m_cpu, &epll_792m,
							&cpll_p},
	.prediv             = 1,
	.sel_reg_offset     = VA_CPU_SYS_APB_REG_BASE + 0xc,
	.sel_reg_mask       = 0x3,
	.en_reg_offset      = VA_CPU_SYS_APB_REG_BASE + 0x38,
	.en_reg_mask        = 0x4,
};
static struct fh_clk cpu_mtx_clk = {
	.name               = "cpu_mtx_clk",
	.parent             = {&cpu_clk},
	.prediv             = 1,
	.div_reg_offset     = VA_CPU_SYS_APB_REG_BASE + 0xc,
	.div_reg_mask       = 0x380,
	.en_reg_offset      = VA_CPU_SYS_APB_REG_BASE + 0x38,
	.en_reg_mask        = 0x1,
};


static struct fh_clk mcu_clk = {
	.name               = "mcu_clk",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NOGATE | CLOCK_NODIV,
	.parent             = {&osc_clk, &cpll_r, &vpll_648m,
							&epll_792m},
	.prediv             = 1,
	.sel_reg_offset     = VA_CPU_SYS_APB_REG_BASE + 0xc,
	.sel_reg_mask       = 0xc00,
};

static struct fh_clk mcu_mtx_clk = {
	.name               = "mcu_mtx_clk",
	.flag               = CLOCK_NOGATE,
	.parent             = {&mcu_clk},
	.prediv             = 1,
	.div_reg_offset     = VA_CPU_SYS_APB_REG_BASE + 0xc,
	.div_reg_mask       = 0x7000,
};


static struct fh_clk dma0_clk = {
	.name               = "dma0_clk",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&osc_clk, &mpll_50m_cpu, &epll_100m_cpu,
							&epll_200m_cpu},
	.prediv             = 1,
	.sel_reg_offset     = VA_CPU_SYS_APB_REG_BASE + 0xc8,
	.sel_reg_mask       = 0xc00,
	.en_reg_offset      = VA_CPU_SYS_APB_REG_BASE + 0x54,
	.en_reg_mask        = 0x2,
};
static struct fh_clk dma1_clk = {
	.name               = "dma1_clk",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&osc_clk, &mpll_50m_cpu, &epll_100m_cpu,
							&epll_200m_cpu},
	.prediv             = 1,
	.sel_reg_offset     = VA_CPU_SYS_APB_REG_BASE + 0xc8,
	.sel_reg_mask       = 0xc00,
	.en_reg_offset      = VA_CPU_SYS_APB_REG_BASE + 0x54,
	.en_reg_mask        = 0x1,
};

static struct fh_clk gmac_mtx = {
	.name               = "gmac_mtx",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV | CLOCK_NOGATE,
	.parent             = {&osc_clk, &mpll_50m_vdu, &epll_100m_vdu,
							&epll_200m_vdu},
	.prediv             = 1,
	.sel_reg_offset     = VA_VDU_SYS_APB_REG_BASE + 0x0,
	.sel_reg_mask       = 0x30,
};

static struct fh_clk pixel_hkisp_sc = {
	.name               = "pixel_hkisp_sc",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&vpll_13m_vdu, &mpll_22m_vdu, &osc_clk,
							&vpll_40m_vdu},
	.prediv             = 1,
	.en_reg_offset		= VA_VDU_SYS_APB_REG_BASE + 0x0,
	.en_reg_mask		= 0x4000,
	.sel_reg_offset     = VA_VDU_SYS_APB_REG_BASE + 0x0,
	.sel_reg_mask       = 0xc0,
};

static struct fh_clk pixel_hkisp = {
	.name               = "pixel_hkisp",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&vpll_13m_vdu, &mpll_22m_vdu, &osc_clk,
							&vpll_40m_vdu},
	.prediv             = 1,
	.sel_reg_offset     = VA_VDU_SYS_APB_REG_BASE + 0x0,
	.sel_reg_mask       = 0xc0,
	.div_reg_offset     = VA_VDU_SYS_APB_REG_BASE + 0x0,
	.div_reg_mask       = 0xfe000000,
	.en_reg_offset      = VA_NNP_SYS_APB_REG_BASE + 0x0,
	.en_reg_mask        = 0x80,
};

static struct fh_clk driver_hkisp = {
	.name               = "driver_hkisp",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&mpll_22m_vdu, &osc_clk,  &vpll_27m_vdu,
							&vpll_40m_vdu},
	.prediv             = 1,
	.sel_reg_offset     = VA_VDU_SYS_APB_REG_BASE + 0x0,
	.sel_reg_mask       = 0x18000,
	.en_reg_offset      = VA_NNP_SYS_APB_REG_BASE + 0x0,
	.en_reg_mask        = 0x20000,
};
#if 0
static struct fh_clk disp_hkisp = {
	.name               = "disp_hkisp",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&osc_clk,  &vpll_3m_vdu, &vpll_40m_vdu,
							&vpll_54m_vdu},
	.prediv             = 1,
	.sel_reg_offset     = VA_VDU_SYS_APB_REG_BASE + 0x0,
	.sel_reg_mask       = 0x18000,
	.en_reg_offset      = VA_NNP_SYS_APB_REG_BASE + 0x0,
	.en_reg_mask        = 0x20000,
};
#endif
static struct fh_clk sdc1_clk = {
	.name               = "sdc1_clk",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&osc_clk, &nnp_50m, &nnp_200m,
							&nnp_400m},
	.prediv             = 1,
	.sel_reg_offset     = VA_VDU_SYS_APB_REG_BASE + 0x0,
	.sel_reg_mask       = 0xc0000,
	.en_reg_offset      = VA_VDU_SYS_APB_REG_BASE + 0x0,
	.en_reg_mask        = 0x300000,
};

static struct fh_clk sadc_clk = {
	.name               = "sadc_clk",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&osc_clk, &nnp_50m, &nnp_200m,
							&nnp_400m},
	.prediv             = 1,
	.sel_reg_offset     = VA_VDU_SYS_APB_REG_BASE + 0x8,
	.sel_reg_mask       = 0xc0000,
	.div_reg_offset     = VA_VDU_SYS_APB_REG_BASE + 0x8,
	.div_reg_mask       = 0x1fc0,
	.en_reg_offset      = VA_VDU_SYS_APB_REG_BASE + 0x8,
	.en_reg_mask        = 0x100000,
};

static struct fh_clk emmc_clk = {
	.name               = "emmc_clk",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&osc_clk, &nnp_50m, &nnp_200m,
							&nnp_400m},
	.prediv             = 1,
	.sel_reg_offset     = VA_NNP_SYS_APB_REG_BASE + 0x200,
	.sel_reg_mask       = 0x3,
	.div_reg_offset     = VA_NNP_SYS_APB_REG_BASE + 0x200,
	.div_reg_mask       = 0x7f000000,
	.en_reg_offset      = VA_NNP_SYS_APB_REG_BASE + 0x200,
	.en_reg_mask        = 0xfc0000,
	.def_rate           = 50000000,
};

static struct fh_clk emmc_2x_clk = {
	.name               = "emmc_2x_clk",
	.flag               = CLOCK_MULTI_PARENT,
	.parent             = {&osc_clk, &nnp_50m, &nnp_200m,
							&nnp_400m},
	.prediv             = 1,
	.sel_reg_offset     = VA_NNP_SYS_APB_REG_BASE + 0x204,
	.sel_reg_mask       = 0xc,
	.div_reg_offset     = VA_NNP_SYS_APB_REG_BASE + 0x204,
	.div_reg_mask       = 0x1fc0,
	.en_reg_offset      = VA_NNP_SYS_APB_REG_BASE + 0x204,
	.en_reg_mask        = 0x10,
	.def_rate           = 200000000,
};
static struct fh_clk emmc_apb_gate = {
	.name               = "emmc_apb_gate",
	.flag               = CLOCK_NORESET|CLOCK_NODIV,
	.prediv             = 1,
	.en_reg_offset      = VA_NNP_SYS_APB_REG_BASE + 0x204,
	.en_reg_mask        = 0x20,
};

static struct fh_clk usb_clk = {
	.name               = "usb_clk",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&rtc_32k, &nnp_20m, &osc_clk,
						&nnp_50m, &nnp_100m},
	.prediv             = 1,
	.sel_reg_offset     = VA_NNP_SYS_APB_REG_BASE + 0x300,
	.sel_reg_mask       = 0x70,
	.en_reg_offset      = VA_NNP_SYS_APB_REG_BASE + 0x300,
	.en_reg_mask        = 0xd,
};

static struct fh_clk usb3_clk = {
	.name               = "usb3_clk",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&rtc_32k, &nnp_20m, &osc_clk,
						&nnp_50m, &nnp_100m},
	.prediv             = 1,
	.sel_reg_offset     = VA_NNP_SYS_APB_REG_BASE + 0x400,
	.sel_reg_mask       = 0xe000,
	.en_reg_offset      = VA_NNP_SYS_APB_REG_BASE + 0x400,
	.en_reg_mask        = 0xd1020,
};


static struct fh_clk sdc0_clk = {
	.name               = "sdc0_clk",
	.flag               = CLOCK_MULTI_PARENT | CLOCK_NODIV,
	.parent             = {&osc_clk, &nnp_50m, &nnp_100m,
							&nnp_200m},
	.prediv             = 1,
	.sel_reg_offset     = VA_NNP_SYS_APB_REG_BASE + 0x500,
	.sel_reg_mask       = 0x18,
	.en_reg_offset      = VA_NNP_SYS_APB_REG_BASE + 0x500,
	.en_reg_mask        = 0x23,
};

/*ckg_glb_isp_en/ckg_glb_apb_en*/
static struct fh_clk isp = {
	.name               = "isp",
	.flag               = CLOCK_NORESET|CLOCK_NODIV,
	.prediv             = 1,
	.en_reg_offset		= VA_CEN_GLB_APB_REG_BASE + 0x78,
	.en_reg_mask		= 0x2000000,
};
/*ckg_glb_vicap_en*/

static struct fh_clk vicap = {
	.name               = "vicap",
	.flag               = CLOCK_NORESET|CLOCK_NODIV,
	.prediv             = 1,
	.en_reg_offset		= VA_CEN_GLB_APB_REG_BASE + 0x78,
	.en_reg_mask		= 0x10000000,
};
/*ckg_glb_apb_veu_en*/
static struct fh_clk glb_apb_veu = {
	.name               = "glb_apb_veu",
	.flag               = CLOCK_NORESET|CLOCK_NODIV,
	.prediv             = 1,
	.en_reg_offset		= VA_CEN_GLB_APB_REG_BASE + 0x78,
	.en_reg_mask		= 0x8,
};
/*ckg_apb_veu_en*/
static struct fh_clk apb_veu = {
	.name               = "apb_veu",
	.flag               = CLOCK_NORESET|CLOCK_NODIV,
	.prediv             = 1,
	.en_reg_offset		= VA_VEU_SYS_AHB_REG_BASE + 0x0,
	.en_reg_mask		= 0x1,
};
/*ckg_glb_veu_en*/
static struct fh_clk veu = {
	.name               = "veu",
	.flag               = CLOCK_NORESET|CLOCK_NODIV,
	.prediv             = 1,
	.en_reg_offset		= VA_CEN_GLB_APB_REG_BASE + 0x78,
	.en_reg_mask		= 0x1000000,
};
/*ckg_glb_apb_vdu_en*/
static struct fh_clk glb_apb_vdu = {
	.name               = "glb_apb_vdu",
	.flag               = CLOCK_NORESET|CLOCK_NODIV,
	.prediv             = 1,
	.en_reg_offset		= VA_CEN_GLB_APB_REG_BASE + 0x78,
	.en_reg_mask		= 0x1,
};
/*ckg_glb_vdu_vdu_en*/
static struct fh_clk glb_vdu_vdu = {
	.name               = "glb_vdu_vdu",
	.flag               = CLOCK_NORESET|CLOCK_NODIV,
	.prediv             = 1,
	.en_reg_offset		= VA_CEN_GLB_APB_REG_BASE + 0x78,
	.en_reg_mask		= 0x200,
};
/*ckg_glb_vdu_en*/
static struct fh_clk glb_vdu_en = {
	.name               = "glb_vdu_en",
	.flag               = CLOCK_NORESET|CLOCK_NODIV,
	.prediv             = 1,
	.en_reg_offset		= VA_CEN_GLB_APB_REG_BASE + 0x78,
	.en_reg_mask		= 0x8000000,
};
/*ckg_glb_vou_vdu_en*/
static struct fh_clk vou_vdu_en = {
	.name               = "vou_vdu_en",
	.flag               = CLOCK_NORESET|CLOCK_NODIV,
	.prediv             = 1,
	.en_reg_offset		= VA_CEN_GLB_APB_REG_BASE + 0x78,
	.en_reg_mask		= 0x800,
};
/*ckg_glb_vou_en*/
static struct fh_clk glb_vou_en = {
	.name               = "glb_vou_en",
	.flag               = CLOCK_NORESET|CLOCK_NODIV,
	.prediv             = 1,
	.en_reg_offset		= VA_CEN_GLB_APB_REG_BASE + 0x78,
	.en_reg_mask		= 0x4000000,
};
/*ckg_jpg_ug_en*/
static struct fh_clk jpg_ug_en = {
	.name               = "jpg_ug_en",
	.flag               = CLOCK_NORESET|CLOCK_NODIV,
	.prediv             = 1,
	.en_reg_offset		= VA_VDU_SYS_APB_REG_BASE + 0x8,
	.en_reg_mask		= 0x80000000,
};
/*ckg_vppu_en*/
static struct fh_clk vppu_en = {
	.name               = "vppu_en",
	.flag               = CLOCK_NORESET|CLOCK_NODIV,
	.prediv             = 1,
	.en_reg_offset		= VA_VDU_SYS_APB_REG_BASE + 0x8,
	.en_reg_mask		= 0x40000000,
};
/*ckg_glb_apb_nnp_en*/
static struct fh_clk glb_apb_nnp = {
	.name               = "glb_apb_nnp",
	.flag               = CLOCK_NORESET|CLOCK_NODIV,
	.prediv             = 1,
	.en_reg_offset		= VA_CEN_GLB_APB_REG_BASE + 0x78,
	.en_reg_mask		= 0x2,
};
/*nnp_iso_en*/
static struct fh_clk nnp_iso_en = {
	.name               = "nnp_iso_en",
	.flag               = CLOCK_NORESET|CLOCK_NODIV,
	.prediv             = 1,
	.en_reg_offset		= VA_NNP_SYS_APB_REG_BASE + 0x0,
	.en_reg_mask		= 0x20000,
};

static struct fh_clk sdc0_clk_sample = {
	.name               = "sdc0_clk_sample",
	.parent             = {&sdc0_clk},
	.flag				= CLOCK_NOGATE | CLOCK_PHASE,
	.prediv             = 1,
	.sel_reg_offset     = VA_CEN_GLB_APB_REG_BASE + 0x78,
	.sel_reg_mask       = 0x2,
};

static struct fh_clk sdc0_clk_drv = {
	.name               = "sdc0_clk_drv",
	.parent             = {&sdc0_clk},
	.flag				= CLOCK_NOGATE | CLOCK_PHASE,
	.prediv             = 1,
	.sel_reg_offset     = VA_NNP_SYS_APB_REG_BASE + 0x504,
	.sel_reg_mask       = 0x80,
};

static struct fh_clk sdc1_clk_sample = {
	.name               = "sdc1_clk_sample",
	.parent             = {&sdc1_clk},
	.flag				= CLOCK_NOGATE | CLOCK_PHASE,
	.prediv             = 1,
	.sel_reg_offset     = VA_VDU_SYS_APB_REG_BASE + 0x104,
	.sel_reg_mask       = 0x2,
};

static struct fh_clk sdc1_clk_drv = {
	.name               = "sdc1_clk_drv",
	.parent             = {&sdc1_clk},
	.flag				= CLOCK_NOGATE | CLOCK_PHASE,
	.prediv             = 1,
	.sel_reg_offset     = VA_VDU_SYS_APB_REG_BASE + 0x104,
	.sel_reg_mask       = 0x80,
};


struct fh_clk *fh_clks[] = {
	&osc_clk,
	&osc_1m,
	&rtc_32k,
	&upll_p,
	&upll_r,
	&epll_p,
	&epll_r,
	&vpll_p,
	&vpll_r,
	&mpll_p,
	&mpll_r,
	&cpll_p,
	&cpll_r,
	&dpll_p,
	&dpll_r,
	&dpll_792m,
	&epll_792m,
	&mpll_450m,
	&vpll_648m,
	&upll_1536m,
	&spll_297m,
	&vpll_324m_top,
	&mpll_50m_top,
	&mpll_25m_top,
	&upll_768m_top,
	&upll_512m_top,
	&upll_128m_top,
	&upll_48m_top,
	&epll_400m_top,
	&epll_200m_top,
	&epll_100m_top,
	&epll_400m_dmc,
	&mpll_50m_dmc,
	&vpll_324m_vdu,
	&vpll_54m_vdu,
	&vpll_40m_vdu,
	&vpll_27m_vdu,
	&vpll_13m_vdu,
	&mpll_50m_vdu,
	&mpll_25m_vdu,
	&mpll_22m_vdu,
	&mpll_15m_vdu,
	&epll_400m_vdu,
	&epll_200m_vdu,
	&epll_100m_vdu,
	&epll_67m_vdu,
	&upll_128m_vdu,
	&nnp_20m,
	&nnp_50m,
	&nnp_100m,
	&nnp_150m,
	&nnp_200m,
	&nnp_400m,
	&nnp_533m,
	&nnp_648m,
	&nnp_768m,
	&nnp_792m,
	&mpll_50m_veu,
	&epll_200m_isp,
	&epll_100m_isp,
	&mpll_50m_isp,
	&vpll_81m_isp,
	&epll_200m_cpu,
	&epll_400m_cpu,
	&epll_100m_cpu,
	&mpll_50m_cpu,
	&tmr0_clk,
	&tmr1_clk,
	&tmr2_clk,
	&pts_clk,
	&ephy_clk,
	&glb_apb,
	&glb_vicap,
	&glb_cpu2lvd,
	&glb_vdu,
	&glb_vou,
	&glb_isp,
	&glb_veu,
	&ave_bond_ave,
	&ahb_ave_bond,
	&ahb_bgm,
	&bgm_clk,
	&g2d_clk,
	&axi_hkisp_mst,
	&ahb_ive,
	&ive_clk,
	&jpeg_clk,
	&ahb_jpeg,
	&kcf_clk,
	&ahb_tve_bond,
	&vou_sif,
	&vou_mif,
	&dsi_pixel_clk,
	&vou_mif_pad_sel,
	&vdec660_bond,
	&vou460_clk,
	&vppu460_clk,
	&nnp_clk,
	&top_apb,
	&sfc_clk,
	&spi0_clk,
	&spi1_clk,
	&syst_clk,
	&uart0_clk,
	&uart1_clk,
	&uart2_clk,
	&uart3_clk,
	&uart4_clk,
	&uart5_clk,
	&i2c0_clk,
	&i2c1_clk,
	&i2c2_clk,
	&i2c3_clk,
	&i2c4_clk,
	&i2c5_clk,
	&pwm_clk,
	&hash_clk,
	&src_clk,
	&rsa_clk,
	&trng_clk,
	&gpio_db_clk,
	&sensor0_clk,
	&sensor1_clk,
	&sensor2_clk,
	&cpu_clk,
	&cpu_mtx_clk,
	&mcu_clk,
	&mcu_mtx_clk,
	&dma0_clk,
	&dma1_clk,
	&gmac_mtx,
	&pixel_hkisp_sc,
	&pixel_hkisp,
	&driver_hkisp,
	&usb_clk,
	&usb3_clk,
	&emmc_clk,
	&emmc_2x_clk,
	&emmc_apb_gate,
	&sdc0_clk,
	&sdc1_clk,
	&sadc_clk,
	&isp,
	&vicap,
	&glb_apb_veu,
	&apb_veu,
	&veu,
	&glb_apb_vdu,
	&glb_vdu_vdu,
	&glb_vdu_en,
	&vou_vdu_en,
	&glb_vou_en,
	&jpg_ug_en,
	&vppu_en,
	&glb_apb_nnp,
	&nnp_iso_en,
	&sdc0_clk_sample,
	&sdc0_clk_drv,
	&sdc1_clk_sample,
	&sdc1_clk_drv,
	NULL,
};
EXPORT_SYMBOL(fh_clks);
